Various techniques have heretofore been used to package integrated circuits. For example, various configurations utilizing lead frames to connect integrated circuits have been developed, such as the flip chip design and the small outline J lead (SOJ) packaging techniques. In many of these prior techniques, the integrated circuit is mounted upon a pad provided by a lead frame, and wire bonds connect from the integrated circuit to conductive leads on the lead frame.
More recently, an integrated circuit packaging technique termed the lead on chip (LOC) technique has been developed for plastic encapsulated packages. As described in the article entitled Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques by William C. Ward, published at the 38th ECC in 1988, this technique disposes a lead frame over the active area of an integrated circuit. Insulating adhesive tape connects the lead frame over the integrated circuit chip, and wire bonds connect the circuit directly to the power buses on the lead frame or jumper over the power buses to conductive leads to provide the correct signal routing. The entire structure, with the exception of the J-shaped lead fingers, is then encapsulated in plastic by molding.
The lead on chip technique provides several advantages over prior packaging techniques. First, the ability to jump wires over various lead frame leads provides significant advantages by allowing alterable package I/O without chip redesign, since the wires can readily be routed over various buses or leads similar to conventional wire bonding as done on direct chip attached circuit cards. The lead on chip technique also provides significant electrical advantages over prior techniques. As chip sizes have increased, on chip busing of power and ground becomes disadvantageous because of high resistance and/or inductance in the on chip bus. High resistance developed in the long lines of thin film aluminum typically used in integrated circuit construction results in unacceptably large voltage drops in the bus. The lead on chip technique permits a comparatively much heavier bus, with a correspondingly much lower resistance, to be fabricated in the lead frame external to the chip. The voltage drop in the bus is thus lowered significantly by use of lead on chip packaging. Bus resistance can be further reduced by providing multiple contacts from chip bond pads to the lead frame bus.
Similarly, bus inductance can be reduced by use of lead frame rather than on chip busing. The lead on chip technique lowers the inductance of the signal, power and ground leads for the package because the lead frame bus has much lower inductance than long bond wires of previous techniques. Furthermore, by providing two pins for power and ground, the inductance is approximately half that of a single lead with multiple contacts.
An additional advantage realized by the lead on chip packaging technique is improved heat dissipation accomplished by the close proximity of the metal lead frame to the chip junctions. Finally, the pin count of a packaged chip may be reduced by use of the lead frame bus with multiple wire bonds to the bus.
An inherent disadvantage exists with current lead on chip designs, however. This arises from the location of lead frame power and ground buses between bond pads on the integrated circuit chip and the inner ends of the signal leads of the lead frame. These locations for the buses require that wire bonds from the chip bond pads to the signal leads must jump or bridge over a power or ground bus, creating a risk of wire bond short circuiting to the bus. The opportunity for shorting may arise from assembly processes such as poor bond location, wire loop control, mold compound sweep, or from accidental touching during processing.
One approach to minimize shorting problems suggests the use of insulated wire. See, Insulated Aluminum Bonding Wire For High Lead Count Packaging by Alex J. Oto, International Journal for Hybrid Microelectronics, Vol. 9, No. 1, 1986. While insulated wire has been reported to have some degree of success in conventional assembly packages, the successful implementation in a lead on chip package is questionable due to the nature of the wire bond stitch as it occurs over the insulating film on top of the integrated circuit. The probability of reliable implementation of insulated wire bonds on a production scale is therefore unlikely. Furthermore, insulated wire is expensive.
The demand for ever higher board density and thinner integrated circuit packaging had lead to another recently developed semiconductor packaging technique known as tape automated bonding (TAB), or tab bonding. The tab bonding technique replaces the traditional lead frame with a one, two, or three layer continuous film, or lead tape, containing conductive lead fingers. The wire bond of lead on chip packaging is replaced with a thermocompression, metallurgical bond between the chip bond pad and the tip of a lead finger. The tab bond requires that the bond pad, the lead finger tip, or both, be "bumped" with a thin metal layer, typically of gold, copper plated with gold, or titanium tungsten and gold, to form a 1 mil thick rectangular bump. Tab bonding is complete when sufficient heat and pressure have been applied to the lead finger and bond pad for a sufficient time period to form a metallurgical bond. See, Overview of Tape Automated Bonding by J. H. Lau, Electronic Materials Handbook, Vol. 1, 1989, p. 275, 285-286.
Tab bonding technology, however, suffers from at least one inherent disadvantage in comparison with conventional lead on chip packaging with wire bonding. Because the signal lead fingers must be brought into physical contact with the integrated circuit chip bond pads, it has heretofore not been feasible to locate power and ground buses on the lead tape adjacent the conductive lead fingers.
A need has thus arisen for a semiconductor packaging apparatus having the recognized advantages of lead on chip packaging and on chip busing, but which does not require that bond wires bridge over the buses, or the use of insulated bonding wire. Preferably, such a packaging apparatus will be adaptable for use with either wire or tab bonding techniques.